this page covers chapter 4. but some of terms and concepts was already covered in Logic Circuits


  • A single cycle processor is a processor that carries out one instruction in a single clock cycle. (that is )

  • These are the instructions we will implement:

    • R-type instructions: add, sub, and, or, slt
    • I-type instructions: lw, sw, beq
    • J-type instructions: j

  1. Fetch
  2. Decode
  3. Execute
  4. Memory
  5. Write Back

Logic Design Conventions

  • Datapath elements are classified into two types:

  • clock methodology: edge-triggered (positive, rising edge)

  • nearly all elements are 32-bit wide

  • buses are indicated with thicker lines

Control

Main Control Unit

  • Input: 6-bit opcode (instruction[31-26])
  • Output:
    • RegDst: Whether write to register rt (0) or rd (1)
    • RegWrite: Whether Write register register is written with Write data value
    • ALUSrc:
      • 1 = the 2nd ALU operand is the sign-extended 16-bit immediate value,
      • 0 = the 2nd ALU operand comes from the 2nd register file output (Read data 2)
    • MemRead: 1 = read from memory
    • MemWrite: 1 = write to memory
    • MemtoReg:
      • 0 = the ALU result is written to the register file
      • 1 = the memory data is written to the register file
    • Branch: 1 = branch
    • ALUOp: 2-bit control signal for ALU operation
    • Jump: 1 = jump, 0 = don’t jump
Instr.OpcodeRegDstALUOp1ALUOp0ALUSrcBranchMemReadMemWriteRegWriteMemtoRegJump
R000000 (0)1100000100
lw100011 (35)0001010110
sw101011 (43)X0010010X0
beq000100 (4)X0101000X0
addi001000 (8)0001000100
j000010 (2)XXXXX000X1
jm0x3f=111111X0011100X1

ALU Control Unit

Determine the 4-bit ALU control signal based on ALUOp signals and funct code.

  • Input:
    • : 1-bit control signal (from the control unit)
    • : 1-bit control signal (from the control unit)
    • : 6-bit function code (from instruction[5-0])
  • Output:
    •  4-bit control signal for ALU operation (will be used to determine as the ALU operation in the ALU)
Input 1Input 2Output
opcodeFunct ()Instruction OperationOperation
00LW, SWXXXXXXload,store0010add
01beqXXXXXXbranch equal0110sub
10R100000add0010add
10R100010subtract0110sub
10R100100AND0000and
10R100101OR0001or
10R101010slt0111slt

Datapath

Instruction Memory

Register File

Data Memory

ALU